San Jose, Calif. — MAX II is a 0.18-micron process CPLD family optimized for communication applications. MAX II CPLD architecture includes an array of LUT-based logic array blocks, a bank of ...

Some CPLD device architectures allow you to assign product terms to individual macrocells-product-term steering-and allocate the same product term to multiple macrocells-product-term sharing. The ...

These programmable-logic devices combine CPLD flash configurability with an FPGA lookup-table architecture for lower-cost, logic-intensive designs.

The FPGA architecture incorporates high flip-flop to logic ratio making it ideal for register intensive applications. Also, the FPGA architecture is more granular compared to CPLD architecture making ...

The ispMACH 4000ZE family is a new generation, ultra low power CPLD family based on Lattice’s highly successful ispMACH 4000 CPLD architecture.

FPGAs usually have more flexible interconnection than a CPLD. From a practical standpoint, though, you can consider a CPLD as a “little” FPGA.

The guys over at hackshed have been busy. [Carl] is making programmable logic design easy with an 8 part CPLD tutorial. (March 2018: Link dead. Try the Wayback Machine.) Programmable logic devices… ...